1. Field of the Invention
The present invention relates to a field-effect transistor including an off-set sidewall and a sidewall and a method for fabricating the field-effect transistor.
2. Description of the Prior Art
With reduction in the design rule of semiconductor devices, the degree of integration of circuits has been remarkably increased. It is currently possible to mount more than a hundred million field-effect (MOS) transistors on a single chip. To achieve such a chip, not only the development of superfine processing technology, such as lithography, etching or the like, which requires processing accuracy of several tens nanometer order is necessary but also a transistor structure suitable for each of an n-channel MOS transistor and a p-channel MOS transistor has to formed.
As for MOS transistors, conventionally, MOS transistors in which an offset sidewall or a sidewall is formed on each side surface of a gate electrode have been used. Referring to an example in which an offset sidewall is formed, a method for forming an offset sidewall will be briefly described.
First, a gate electrode is formed on a semiconductor substrate, and then an insulation film typified by a silicon oxide film is deposited over a wafer. Subsequently, using a technique such as dry etching and the like, an offset sidewall is formed of an insulator on each of side surfaces of the gate electrode.
However, when an offset sidewall is formed according to the above-described method, an offset sidewall of an n-channel MOS transistor and an offset sidewall of a p-channel MOS transistor have the same thickness. Normally, arsenic, which is hardly diffused by heat, is used in implantation for forming source/drain extensions of an n-channel MOS transistor. On the other hand, boron, which is easily diffused by heat, is used in implantation for forming source/drain extensions of a p-channel MOS transistor. When a transistor is formed, heat treatment typified by impurity activation annealing is simultaneously performed to n-channel and p-channel MOS transistors. Therefore, for example, when an offset sidewall is formed so as to be suitable for an n-channel MOS transistor, the offset sidewall has a small thickness. Then, if an offset sidewall having a small thickness is used for a p-channel MOS transistor, boron overlaps in a wide range under a gate electrode and a transistor of which characteristics are largely degraded due to a short channel effect is formed. In contrast, when an offset sidewall is formed for a p-channel MOS transistor so as to have a large thickness, an amount of boron overlapping is small and an n-channel MOS transistor is offset somewhat. This causes reduction of driving current.
In the transistor generation with a relatively large gate length, an amount of an impurity overlapping under a gate electrode can be adjusted by controlling a dose of an impurity to be implanted or the like. However, in the transistor generation with a very small gate length of 45 nm, 32 nm or the like, the impurity overlapping amount has to be adjusted in a several nanometer order and it is difficult to adjust the impurity overlapping amount only by controlling a dose of an impurity to be implanted. Therefore, formation of a dual offset sidewall which allows optimization for both of an n-channel MOS transistor and a p-channel MOS transistor is desired.
A known method for forming a dual offset sidewall will be described with reference to FIGS. 7A through 7D (see Japanese Laid-Open Publication No. 2004-303789). FIGS. 7A through 7D are cross-sectional views illustrating respective steps for forming a dual offset sidewall according to the known method.
First, as shown in FIG. 7A, a first gate insulation film 1301a and a first gate electrode 1302a of polysilicon are formed in a region (NMOS formation region) of a semiconductor substrate 1300 and a second gate insulation film 1301b and a second gate electrode 1302b of polysilicon are formed in another region (PMOS formation region) of the semiconductor substrate 1300.
Subsequently, as shown in FIG. 7B, an offset sidewall insulation film 1303 of a silicon oxide film or the like is deposited over a surface of the semiconductor substrate to a thickness of 10 nm.
Next, as shown in FIG. 7C, for example, a resist mask 1304 is provided over the PMOS formation region of the semiconductor substrate 1300 and then an n-type impurity such as arsenic having a relatively large atomic weight is ion implanted 1305 in the entire surface of the semiconductor substrate 1300. In this case, arsenic is ion implanted only in part of the offset sidewall insulation film 1303 located in the NMOS formation region and an insulation film 1306 which has been damaged by the ion implantation is formed. An etching rate of the insulation film 1306 is higher than that of the offset sidewall insulation film 1303 which has not been damaged by the ion implantation. Therefore, as shown in FIG. 7D, in etching back 1307, a thickness of the insulation film 1306 is reduced and an offset sidewall 1308 is formed on surfaces of the first gate electrode 1302a so as to have a smaller thickness than a thickness of an offset sidewall 1309. Thereafter, using the first gate electrode 1302a and the offset sidewall 1308 as a mask, arsenic is ion implanted into the semiconductor substrate 1300 with the PMOS formation region covered, thereby forming a first extension region 1320a. Next, using the second gate electrode 1302b and the offset sidewall 1309 as a mask, boron is ion implanted into the semiconductor substrate 1300 with the NMOS region covered, thereby forming a second extension region 1320b. 